Nonvolatile memory device and method for fabricating the same

ABSTRACT

A method for fabricating a nonvolatile memory device comprises providing a substrate, forming an insulating layer and a conductive layer on the substrate, forming an electrical connection path out of a portion of the conductive layer, through which the conductive layer is electrically connected to the substrate, and gate patterning the insulating layer and the conductive layer.

BACKGROUND

The present disclosure generally relates to semiconductor memory devicesand, more particularly, the present disclosure relates to nonvolatilememory devices and to methods for fabricating nonvolatile memorydevices.

A claim of priority under 35 U.S.C. § 119 is made to Korean PatentApplication No. 2006-97331, filed Oct. 2, 2006, the entire contents ofwhich are hereby incorporated by reference.

In general, semiconductor memory devices are classified into volatilememory devices and nonvolatile memory devices. Volatile memory devicesinclude, for example, a dynamic random access memory (DRAM.) Volatilememory devices have several distinguishing characteristics. For example,the volatile memory devices cannot retain data when power supply isinterrupted. On the other hand, the nonvolatile memory devices canretain written data even if power supply is interrupted. Nonvolatilememory devices include, for example, a flash memory device capable ofelectrically programming and erasing data.

Due to an increase in demand for faster operating but smaller size flashmemory, the integration density of flash memory is continually beingincreased. Furthermore, when a flash memory device is highly integrated,it may be desirable to ensure a predetermined thicknesses of a tunneldielectric layer and a blocking oxide layer. The predetermined thicknessof these layers may help avoid problems associated with cell operationand reliability. In order to ensure a proper thickness of these layers,the integration density of a flash memory device is increased by scalingdown the flash memory device planarly rather than vertically.

As the flash memory device is being scaled down, a density of plasmaused in a dry etching process for gate patterning is continuouslyincreased. This increase in the plasma density may cause theconcentration of an electric field over a small area of the tunnel oxidelayer. This phenomenon may damage the tunnel oxide layer. This plasmadamage of the tunnel oxide layer may lead to various problems such as,for example, a reduction in the reliability of memory cells, a reductionin the data retained within memory cells, etc.

Thus, there is a need for methods and systems to fabricate highintegration density flash memory devices without the undesirable effectsassociated with an increase in plasma density and the like. The presentdisclosure is directed towards overcoming the limitations associatedwith conventional flash memory fabrication methods and systems.

SUMMARY OF THE INVENTION

One aspect of the present disclosure includes a method for fabricating anonvolatile memory device. The method comprises providing a substrate,forming an insulating layer and a conductive layer on the substrate,forming an electrical connection path out of a portion of the conductivelayer, through which the conductive layer is electrically connected tothe substrate, and gate patterning the insulating layer and theconductive layer. Another aspect of the present disclosure includes amethod for fabricating a nonvolatile memory device. The method comprisesproviding a substrate including a cell array region and a dummy patternregion, forming a tunnel oxide layer and a floating gate layer on thesubstrate, forming a first butting contact out of a portion of thefloating gate layer through which the floating gate layer iselectrically connected to the substrate in the dummy pattern region,forming a blocking oxide layer and a control gate layer on the floatinggate layer, and gate patterning the control gate layer, the blockingoxide layer, the floating gate layer, and the tunnel oxide layer to forma word line in the cell array region and a first dummy pattern in thedummy pattern region, wherein the word line extends in a firstdirection, and wherein the first dummy pattern extends in the firstdirection and has the first butting contact.

Yet another aspect of the present disclosure includes a method forfabricating a nonvolatile memory device. The method comprises providinga substrate including a cell array region and a dummy pattern region,forming a charge storage layer and a gate layer on the substrate,forming a butting contact out of a portion of the gate layer throughwhich the gate layer is electrically connected to the substrate in thedummy pattern region, and gate patterning the gate layer and the chargestorage layer to form a word line in the cell array region and a firstdummy pattern in the dummy pattern region, wherein the word line extendsin a first direction, and wherein the first dummy pattern extends in thefirst direction and includes the butting contact.

Yet another aspect of the present disclosure includes a nonvolatilememory device. The nonvolatile memory device includes a substrateincluding a cell array region and a first dummy pattern region, a wordline extending in a first direction in the cell array region, and havinga first insulating layer and a first conductive layer, and a first dummypattern including the first insulating layer, the first conductive layerand a first butting contact formed from a portion of the firstconductive layer, wherein the first butting contact provides anelectrical connection path connecting the first conductive layer to thesubstrate.

Another aspect of the present disclosure includes a nonvolatile memorydevice. The device includes a substrate including a cell array regionand a first dummy pattern region, a word line extending in a firstdirection in the cell array region, and including a first insulatinglayer and a first conductive layer, and a trench formed by removing aportion of the substrate in the first dummy pattern region, andextending in the first direction.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying figures are included to provide a further understandingof the present invention, and are incorporated in and constitute a partof this specification. The drawings illustrate exemplary embodiments ofthe present invention and, together with the description, serve toexplain principles of the present invention. In the figures:

FIG. 1 is a plan view of a nonvolatile memory device according to anexemplary disclosed embodiment;

FIGS. 2A through 2F are sectional views taken along line I-I′ of FIG. 1,illustrating a method for fabricating the nonvolatile memory deviceaccording to an exemplary disclosed embodiment;

FIGS. 3A and 3B are sectional views illustrating a method forfabricating the nonvolatile memory device according to an alternativeexemplary disclosed embodiment;

FIGS. 4A and 4B are sectional views illustrating another alternativeexemplary disclosed embodiment;

FIGS. 5A through 5D are sectional views illustrating a method forfabricating the nonvolatile memory device according to yet anotheralternative exemplary disclosed embodiment;

FIG. 6 is a plan view of a nonvolatile memory device according to analternative exemplary disclosed embodiment;

FIGS. 7A through 7H are sectional views taken along line I-I′ of FIG. 6,illustrating a method for fabricating the nonvolatile memory deviceaccording to an alternative exemplary disclosed embodiment; and

FIGS. 8 through 10 are sectional views taken along line I-I′ of FIG. 6,illustrating a method for fabricating the nonvolatile memory deviceaccording to an alternative exemplary disclosed embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, a nonvolatile memory device and a method for fabricatingthe same it will be fully described with reference to the accompanyingdrawings.

FIG. 1 is a plan view of a nonvolatile memory device according to anexemplary disclosed embodiment. Referring to FIG. 1, the nonvolatilememory device is a flash memory device 10 that performs a programmingoperation by storing charges in a conductor, i.e., a floating gate. Tothis end, the flash memory device 10 includes a cell array region B. Thecell array region B includes a plurality of active regions 101 extendingalong the Y-axis over a substrate 100, and a plurality of word lines 130extending along the X-axis that is substantially perpendicular to theactive regions 101. Furthermore, the active regions 101 are separatedfrom each other by means of a device isolation layer 103. In addition,each of the word lines 130 includes a floating gate that stores charges.Furthermore, the flash memory device 10 includes a dummy pattern regionA having a dummy pattern 140 extending along the X-axis over thesubstrate 100. Specifically, the dummy pattern 140 is a pattern thatminimizes the damage due to plasma by discharging charges into thesubstrate 100 during the plasma dry etching process.

FIGS. 2A through 2F are sectional views taken along line I-I′ of FIG. 1,illustrating a method for fabricating the nonvolatile memory deviceaccording to an exemplary disclosed embodiment.

Referring to FIG. 2A, the flash memory device 10 includes asemiconductor substrate 100 of a first conductive type. In addition, afirst well 102 of a second conductive type is formed in thesemiconductor substrate 100. Furthermore, a second conductive well 104of the first conductive type is formed in the first well 102. Forexample, an n-well 102 is formed in the p-type silicon substrate 100,and a p-well 104 is formed in the n-well 102. Specifically, the p-well104 may be designated as a pocket p-well, and the n-well 102 may bedesignated as a deep n-well. In addition, a first dielectric layer 106,i.e., an insulating layer, is formed over the substrate 100, and a firstconductive layer 108 is sequentially formed on the first dielectriclayer 106. In particular, the first dielectric layer 106 constitutes atunnel insulating layer of the flash memory device 10. In addition, thefirst conductive layer 108 may be formed of polysilicon or metal.Moreover, the first dielectric layer 106 and the first conductive layer108 are formed in both the cell array region B and the dummy patternregion A.

Referring to FIG. 2B, a photoresist pattern 110 is formed on the firstconductive layer 108 by any well-known photolithography process.Furthermore, the photoresist pattern 110 covers the cell array region Bof the substrate 100 and partially exposes the dummy pattern region A.In addition, portions of the first conductive layer 108 and the firstdielectric layer 106 are removed through an etching process using thephotoresist pattern 110 as a mask to form a contact hole 112. Thecontact hole 112 partially exposes a surface of the substrate 100. Whenforming the contact hole 112, the substrate 100 may be over-etched suchthat a bottom surface 112 a of the contact hole 112 is lower than asurface 100 a of the substrate 100. After forming the contact hole 112,first conductive type impurities, e.g., p-type impurities, are implantedinto the substrate 100 through ion implantation using the photoresistpattern 110 as a mask to form a p-well 114 in the substrate 100 underthe contact hole 112. In an exemplary embodiment, a p-type impurityconcentration of the p-well 114 is greater than that of the pocketp-well 104.

Referring to FIG. 2C, the photoresist pattern 110 is removed and asecond conductive layer 116 is formed on the first conductive layer 108.Specifically, when the second conductive layer 116 is formed on thefirst conductive layer 108, the second conductive layer 116 fills thecontact hole 112 to thereby form a butting contact 116′ that directlyconnects the second conductive layer 116 to the substrate 100. That is,the butting contact 116′ serves as a connection path that electricallyconnects the second conductive layer 116 and the substrate 100. In anexemplary embodiment, the second conductive layer 116 may be formed ofpolysilicon or metal. Furthermore, the first and second conductivelayers 108 and 116 constitute the floating gate of the flash memorydevice.

A second dielectric layer 118 is formed on the second conductive layer116, and a third conductive layer 120 is then formed on the seconddielectric layer 118. For example, the third conductive layer 120 may beformed of polysilicon or metal. In addition, the third conductive layer120 constitutes a control gate of the flash memory device. Moreover, thesecond dielectric layer 118 is interposed between the control gate andthe floating gate so that it acts as a blocking dielectric layerpreventing charges stored in the floating gate from being tunneled intothe control gate. In an exemplary embodiment, the second dielectriclayer 118 may be formed of oxide/nitride/oxide (ONO) layer that hassufficient thickness and resistivity against high voltage, and also hasdielectric properties. Furthermore, the ONO layer is configured with anitride layer interposed between the oxide layers.

Referring to FIG. 2D, plasma dry etching is performed for gatepatterning using a photoresist pattern 122 as a mask. To this end, thephotoresist pattern 122 has a shape that is adapted for gate patterning.FIG. 2D shows that the third conductive layer 120 and the seconddielectric layer 118 are selectively removed during the plasma dryetching process thereby forming a third conductive layer pattern 120 aand a second dielectric layer pattern 118 a. However, the secondconductive layer 116 is not patterned. Because the second conductivelayer 116 is not completely etched, plasma charges accumulate in thesecond conductive layer 116. Furthermore, the charges accumulated in thebutting contact 116′ are discharged through the substrate 100. Inparticular, because the p-well 114, that has a higher dopingconcentration than the pocket p-well 104, is formed under the buttingcontact 116′, the charges accumulated in the second conductive layer 116are effectively discharged through the substrate 100.

Referring to FIG. 2E, in an exemplary embodiment, the plasma dry etchingprocess is performed so that the second conductive layer 116 is etchedto form a second conductive layer pattern 116 a. Furthermore, FIG. 2Erepresents a state where the first conductive layer 108 is not patternedyet. Because the first conductive layer 108 is not etched at this time,the charges are accumulated in the first conductive layer 108. Moreover,the charges accumulated in the first conductive layer 108 are dischargedinto the substrate 100 through the butting contact 116′.

Referring to 2F, plasma dry etching is performed to form a firstconductive layer pattern 108 a and a first dielectric layer pattern 106a. In addition, a spacer 124 is formed to thereby form a word line 130in the cell array region B. In an exemplary embodiment, the word line130 has a stacked structure in which the tunnel dielectric layer 106 a,the floating gate 117, the blocking dielectric layer 118 a and thecontrol gate 120 a are sequentially stacked. In addition, a dummypattern 140 is formed in the dummy pattern region A. In particular, thedummy pattern 140 is separated from the word line 130 by gate patterningso that it is electrically isolated. Therefore, the dummy pattern 140does not electrically affect the cell array region B when the device isoperating.

In the above-described exemplary method for fabricating the nonvolatilememory device, with reference to FIGS. 2A through 2F, the floating gate117 configured with the first conductive layer 108 and the secondconductive layer 116 is electrically connected to the substrate 100.Accordingly, plasma charges are discharged into the substrate 100through the floating gate 117 in the gate patterning using the plasmadry etching process.

FIGS. 3A and 3B are sectional views illustrating another exemplaryembodiment for the method for fabricating the nonvolatile memory deviceaccording. Because the embodiment discussed below is similar to thefabrication process of the exemplary embodiment illustrated in FIGS. 2Athrough 2F, the same features will be described in brief or omittedherein, but distinguishing features may be focused on in the followingdescription.

Referring to FIG. 3A, in an exemplary embodiment, a first dielectriclayer 206 and a first conductive layer 208 are sequentially formed on ap-type substrate 200. In particular, the first dielectric layer 206 isformed to a first thickness d1. Furthermore, a pocket p-well 204 isformed in the p-type substrate 200, and a deep n-well 202 is formed tosurround the pocket p-well 204. Moreover, a photoresist pattern 210 isformed on the conductive layer 208 such that it covers a cell arrayregion B but does not cover a portion of the dummy pattern region A. Inaddition, an etching process is performed using the photoresist pattern210 as a mask to form a contact hole 212 in the dummy pattern region A.

When forming the contact hole 212, only a portion of the firstdielectric layer 212 is etched so that the first dielectric layer 206with a second thickness d2 is left remaining below the contact hole 212,wherein the second thickness d2 is smaller than the first thickness d1.The second thickness d2 is a thickness such that charges accumulated ina second conductive layer 216 a are sufficiently tunneled toward thesubstrate 100 with ease during a dry etching process for gatepatterning. Furthermore, an ion implantation process is performed toform a heavily doped p-well 214 under the contact hole 212. Theconcentration of the p-well 214 is typically greater than that of thepocket p-well 204. The processes subsequent to the ion implantationprocess are identical to those illustrated in FIGS. 2C through 2E.

Referring to FIG. 3B, a spacer 224 is formed. Thus, a word line 230 iscompleted in the cell array region B, which is configured with a tunneldielectric layer 206 a, a floating gate 217, a blocking dielectric layer218 a and a control gate 220 a, all of which are stacked in sequence. Inaddition, a dummy pattern 140, which has no electrical effect on thedevice, is formed in the dummy pattern region A.

FIGS. 4A and 4B are sectional views illustrating yet another exemplaryembodiment for the method for fabricating a nonvolatile memory device.The currently disclosed exemplary embodiment is similar to the previousexemplary embodiment illustrated in FIGS. 2A through 2F. Therefore, thesame features will be described in brief or omitted herein, butdistinguishing features may be focused on in this description. Inaddition, the process prior to FIG. 4A is replaced by the description ofFIGS. 2A through 2C.

Referring to FIG. 4A, a photoresist pattern 322 is formed using awell-known photo process. Then, plasma etching is performed using thephotoresist pattern 322 as a mask to form a third conductive layer 320 aand a second dielectric pattern 318 a. Specifically, the photoresistpattern 322, which is formed for gate patterning, opens the dummypattern region A entirely. FIG. 4A shows a state when the secondconductive layer 316 is not completely patterned yet while the plasmadry etching is being performed. Because the second conductive layer 316is not completely etched, the charges due to plasma generation areaccumulated in the second conductive layer 316. These accumulatedcharges in the second conductive layer 316 are discharged into thesubstrate 300 through a butting contact 316′.

Referring to FIG. 4B, plasma dry etching is performed to form a firstconductive layer pattern 308 a and a first dielectric layer pattern 306a. Subsequently, a spacer 324 is formed. Thus, a word line 330 iscompleted in the cell array region B, which is configured with a tunneldielectric layer 306 a, a floating gate 317, a blocking dielectric layer318 a and a control gate 320 a, all of which are stacked in sequence. Inaddition, because there is no mask in the dummy pattern region A, thedummy pattern 240 of FIG. 2F is not formed but only a trench 312 a thatis a portion of the contact hole 312 remains instead.

FIGS. 5A and 5B are sectional views illustrating an alternativeexemplary embodiment for the method for fabricating a nonvolatile memorydevice. This exemplary embodiment relates to a method for fabricating aSONOS memory device that performs a programming operation by storingcharges in an insulating layer disposed between a gate electrode and asubstrate.

Referring to FIG. 5A, an insulating layer 509 is formed on a p-typesubstrate 500. The insulating layer 509 has a multi-stacked structure inwhich a tunnel dielectric layer 506, a charge storage layer 507, and ablocking dielectric layer 508, are sequentially stacked. For example,the insulating layer 509 may be configured with an ONO layer in whichthe tunnel dielectric layer 506 and the blocking dielectric layer 508are formed of oxide and the charge storage layer 507 is formed ofnitride. Furthermore, the programming operation is performed in such amanner that the charges are trapped in the nitride layer. In addition, apocket p-well 504 and a deep n-well 502 are formed in the p-typesubstrate 500. Furthermore, a portion of the insulating layer 509 isremoved by any well-known etching process to form a contact hole 512 inthe dummy pattern region A. In addition, a heavily doped p-well 514 isformed below the contact hole 512, wherein the concentration of theheavily doped p-well 514 may be made greater than that of the pocketp-well 504 by the use of any well-known ion implantation process.

Referring to FIG. 5B, a first conductive layer 516 and a secondconductive layer 518 are formed sequentially. Furthermore, a portion ofthe first conductive layer 516 fills the contact hole 512 to constitutea butting contact 516′. This butting contact 516′ electrically connectsthe first conductive layer 516 to the substrate 500. In an exemplaryembodiment, the first conductive layer 516 and the second conductivelayer 518 constitute a gate electrode, and are formed of polysilicon ormetal.

Referring to FIG. 5C, a plasma dry etching is performed for gatepatterning using a photoresist pattern 520 as a mash. The photoresistpattern 520 is formed by any well-known photo process. FIG. 5C shows astate where the second conductive layer pattern 518 a is formed byplasma dry etching process and the first conductive layer is notpatterned yet. In an exemplary embodiment, the charges accumulated inthe first conductive layer 516 by the plasma dry etching process aredischarged into the substrate 500 through the butting contact 516′.

Referring to FIG. 5D, a spacer 524 is formed after a gate patterningprocess, and a word line 530 is completed in the cell array region B. Inparticular, the word line 530 is shaped such that an insulating layer509 a is interposed between a gate electrode 517 and the substrate 500.Furthermore, a dummy pattern 540, which does not operate electrically,is formed in the dummy pattern region A.

In yet another exemplary embodiment, as illustrated in FIGS. 3A and 3B,the insulating layer 509 a of the dummy pattern region A may be formedthinner than the insulating layer 509 a of the cell array region B. Inaddition, as illustrated in FIGS. 4A and 4B, the photoresist pattern 520may not be formed in the dummy pattern region A during gate patterning,and thus the dummy pattern 540 may not be formed in the dummy patternregion A.

FIG. 6 is a plan view of a nonvolatile memory device 10 according to analternative exemplary disclosed embodiment. Referring to FIG. 6, thenonvolatile memory device 10 (e.g., flash memory device) includes a cellarray region B in which a plurality of active regions 101 extend alongthe Y-axis over a substrate 100, and a plurality of word lines 130extending along the X-axis that is substantially perpendicular to theextending direction of the active regions 101. Furthermore, the activeregions 101 are separated from each other by means of a device isolationlayer 103. In addition, each of the word lines 130 includes a floatinggate that stores charges. Furthermore, the nonvolatile memory device 10includes a first dummy pattern region A having a dummy pattern 140extending along the X-axis over the substrate 100, and a second dummypattern 150 extending along the Y-axis in a second dummy pattern regionC. In an exemplary embodiment, the first dummy pattern 140 plays a rolein discharging plasma charges into the substrate 100 when performing aplasma dry etching process for gate patterning, and a second dummypattern 150 plays a role in discharging plasma charges into thesubstrate 100 during a plasma dry etching process after the gatepatterning.

FIGS. 7A through 7H are sectional views taken along line I-I′ of FIG. 6,illustrating a method for fabricating the nonvolatile memory deviceaccording to an exemplary disclosed embodiment.

Referring to FIG. 7A, a deep n-well 102 is formed in a p-typesemiconductor substrate 100, and a pocket p-well 104 is formed insidethe deep n-well 102. Furthermore, a first dielectric layer 106 is formedon the p-type substrate 100, and a first conductive layer 108 issequentially formed on the first conductive layer 108. The firstdielectric layer 106 constitutes a tunnel dielectric layer of thenonvolatile memory device, for example, the flash memory device.Furthermore, the first conductive layer 108 is formed of, for example,polysilicon or metal. Moreover, the first dielectric layer 106 and thefirst conductive layer 108 are formed over the substrate 100 in both thecell array region B and the first and second dummy pattern regions A andC, respectively.

Referring to FIG. 7B, a photoresist pattern 110 is formed on the firstconductive layer 108 using any well-known photo process. The photoresistpattern 110 has a shape such that it coves the cell array region B ofthe substrate 100 but partially opens the first and second dummy patternregions A and C. Furthermore, portions of the first conductive layer 108and the first dielectric layer 106 are removed by an etching processusing the photoresist pattern 110 as a mask, thereby forming first andsecond contact holes 112 and 113, respectively. These first and secondholes 112 and 113, respectively, partially expose a surface of thesubstrate 100 in the first and second dummy pattern regions A and B,respectively. In addition, in forming the first contact hole 112, thesubstrate 100 may be over-etched such that a bottom surface 112 a of thefirst contact hole 112 is disposed lower than a surface 100 a of thesubstrate 100. Likewise, a bottom surface 113 a of the second contacthole 113 may be lower than the surface 100 a of the substrate 100.

After forming the first and second contact holes 112 and 113, an ionimplantation process is performed using the photoresist pattern 110 as amask to form a first p-well 114 under the first contact hole 112.Typically, the p-type impurity concentration of the p-well 114 isgreater than the p-type impurity concentration of the pocket p-well 104.Likewise, a heavily doped second p-well 115 is formed under the secondcontact hole 113.

Referring to FIG. 7C, the photoresist pattern 110 is removed, and asecond conductive layer 116 is then formed on the first conductive layer108. Furthermore, when the second conductive layer 116 is formed on thefirst conductive layer 108, the second conductive layer 116 is filledinto the first and second contact holes 112 and 113. Therefore, firstand second butting contacts 116′ and 116″ connecting the secondconductive layer 116 to the substrate 100 are formed in the first andsecond dummy pattern regions A and B, respectively. That is, the firstand second butting contacts 116′ and 116″, respectively, act asconnection paths that electrically connect the second conductive layer116 to the substrate 100. In an exemplary embodiment, the secondconductive layer 116 may be formed of, for example, polysilicon ormetal. Furthermore, the first and second conductive layers 108 and 116constitute a floating gate of the flash memory device.

A second dielectric layer 118 is formed on the second conductive layer116. Specifically, the second dielectric layer 118 is interposed betweenthe control gate and the floating gate, and serves as a blockingdielectric layer preventing the charges stored in the floating gate frombeing tunneled into the control gate. In an exemplary embodiment, thesecond dielectric layer 118, i.e., the blocking dielectric layer may beconfigured as ONO layer in which a nitride layer is interposed betweenoxide layers. Moreover, a potion of the second dielectric layer 118 isremoved to form a third contact hole 119 that exposes a portion of thesecond conductive layer 116 in the second dummy pattern region C. Inaddition, the second conductive layer 116 may be over-etched when thethird contact hole 119 is formed.

Referring to FIG. 7D, a third conductive layer 120 is formed on thesecond conductive layer 118. When forming the third conductive layer120, the third conductive layer 120 fills the third contact hole 119 toform a third butting contact 120′. The third butting contact 120′electrically connects the third conductive layer 120 to the secondconductive layer 116. Therefore, the third conductive layer 120 iselectrically connected to the substrate 100 through the third buttingcontact 120′ and the second butting contact 116″. In an exemplaryembodiment, the third conductive layer 120 may be formed of polysiliconor metal. Furthermore, the third conductive layer 120 constitutes acontrol gate of the flash memory device.

Referring to FIG. 7E, a photoresist pattern 122 is formed using anywell-known photo process. In an exemplary embodiment, the photoresistpattern 122 has a shape adaptive for gate patterning. Furthermore, dryetching is performed for gate patterning using the photoresist pattern122 as a mask. To this end, FIG. 7E shows that a third conductive layerpattern 120 a and a second dielectric layer pattern 118 a are formed andthe second conductive layer is not patterned yet. Because the secondconductive layer 116 is not patterned and is formed on an entire surfaceof the substrate 100, the charges generated due to plasma areaccumulated in the second conductive layer 116. In addition, the chargesaccumulated in the second conductive layer 116 are discharged into thesubstrate 100 through the first and second butting contacts 116′ and116″. Because the first and second butting contacts 116′ and 116″ havethe first and second p-wells 114 and 115 doped with p-type impuritythereunder, wherein the concentrations of the first and second p-wells114 and 115 are greater than the pocket p-well 104, the chargesaccumulated in the second conductive layer 116 are effectivelydischarged into the substrate 100.

Referring to FIG. 7F, the plasma dry etching is performed so that thesecond conductive layer 116 is selectively etched to form a secondconductive layer pattern 116 a. FIG. 7F shows a state where the firstconductive layer 108 is not patterned and formed on entire surface ofthe substrate 100. Therefore, the charges generated by plasma areaccumulated on the first conductive layer 108. Furthermore, the chargesaccumulated in the first conductive layer 108 are discharged into thesubstrate 100 through the first and second butting contacts 116′ and116″.

Referring to FIG. 7G, the plasma dry etching is performed to form afirst conductive layer pattern 108 a and a first dielectric layerpattern 106 a. Furthermore, when forming a spacer 124 by depositing andetching the insulating layer, a word line 130 is formed in a cell arrayregion B. Specifically, the word line 130 is configured with a tunneldielectric layer 106 a, a floating gate 117, a blocking dielectric layer118 a and a control gate 120 a, all of which are stacked in sequence. Inaddition, a first dummy pattern 140 is formed in the first dummy patternregion A. Because the first dummy pattern 140 is electrically isolated,it has no effect on the cell array region B during device operation.

When using the plasma dry etching for forming the spacer 124, thecharges generated by plasma are accumulated in the third conductivelayer pattern 120 a. These charges which are accumulated in the thirdconductive layer pattern 120 a, flow into the floating gate 117 throughthe third butting contact 120′, and are discharged into the substrate100 through the second butting contact 116″.

The control gate 120 a and the floating gate 117 are electricallyconnected to the substrate 100 through the third and second buttingcontacts 120′ and 116″, respectively, formed in the second dummy patternregion C. Furthermore, the plasma charges accumulated in the floatinggate 117 are discharged into the substrate 100 through the first buttingcontact 116′ formed in the first dummy pattern region A during the gatepatterning process. After the gate patterning, the plasma chargesaccumulated in the control gate 120 a are discharged into the substrate100 through the third and second butting contacts 120′ and 116″. Due tothis discharge of plasma charges into the substrate 100, there may be areduction in the possibility of a plasma attack.

Referring to FIG. 7H, the first dummy pattern 140 is separated from theword line 130 during the gate patterning, but the second dummy pattern150 stays connected to the word line 130. Therefore, a portion of theword line 130 adjacent to the second dummy pattern region C, is cut toform the second dummy pattern 150 such that is electrically isolated(see line II-II′ of FIG. 6). The second dummy pattern 150 that is nowelectrically isolated has no effect on the cell array region B.

The method for fabricating the nonvolatile memory device as illustratedin FIGS. 7A through 7H can be applied to the method for fabricating aNAND flash memory device. When fabricating the NAND flash memory deviceby employing the method of FIGS. 7A through 7H, the contact forelectrically connecting the control gate to the floating gate in theselect and ground gates is formed at the same time when the thirdbutting contact 120′ of FIG. 7D is formed.

FIGS. 8 through 10 are sectional views taken along line I-I′ of FIG. 6,illustrating alternative exemplary embodiments of the method forfabricating the nonvolatile memory device, that are similar to theexemplary embodiments discussed above. Therefore, features similar tothose discussed above will be described briefly or omitted herein, butdissimilar features may be focused on in the following description.

Referring to FIG. 8, a first butting contact 616′ and a second buttingcontact 616″ are formed in the first and second dummy pattern regions Aand C, respectively. In addition, a third butting contact 620′ is formedin the second dummy pattern region C for electrically connecting acontrol gate 620 a to a floating gate 617. Moreover, a heavily dopedfirst p-well 614 is formed in a substrate 600 under the first buttingcontact 616′, and a heavily doped second p-well 615 is also formed inthe substrate 600 under the second butting contact 616″.

Similarly to FIGS. 3A and 3B, a thickness d2 of the tunnel dielectriclayer 606 a in the first dummy pattern region A and a thickness d3 ofthe tunnel dielectric layer 606 a in the second dummy pattern region Care smaller than a thickness d1 of the tunnel dielectric layer 606 a.That is, only a portion of the tunnel dielectric layer 606 a is etchedwhen forming the first and second contact holes 612 and 613. In anexemplary embodiment, the thickness d2 of the tunnel dielectric layer606 a under the first contact hole 612 may be equal to the thickness d3of the tunnel dielectric layer 606 a under the second contact hole 613.Furthermore, the thicknesses d1 and d3 are sufficiently small such thatthe plasma charges are easily tunneled during the plasma dry etching forgate patterning.

In an alternative exemplary embodiment, as shown in FIGS. 9A and 9B,only a trench 712 a remains in the first dummy pattern region A.Furthermore, similar to FIGS. 4A and 4B, a dummy pattern 750 having noelectrical effect is formed in the second dummy pattern region C.

Referring to FIG. 9A, a first butting contact 716′ is formed in thefirst dummy pattern region A, and second and third butting contacts 716″and 720′ are formed in the second dummy pattern region C. Furthermore, aplasma dry etching process for gate patterning is performed using aphotoresist pattern 722. Furthermore, the photoresist pattern 722, whichacts as a mask, exposes the first dummy pattern region A. In addition,plasma charges are accumulated in the second and first conductive layers716 and 708, and are discharged into the substrate 700 through the firstbutting contact 716′. Moreover, the plasma charges are discharged intothe substrate 700 through the third and second butting contacts 720′ and716″.

FIG. 10 illustrates another alternative exemplary embodiment forfabricating a memory device. Specifically referring to FIG. 10, thisexemplary embodiment relates to the method for fabricating a SONOSmemory device similar to FIGS. 5A through 5D. In particular, a firstdummy pattern 840 is formed in the first dummy pattern region A fordischarging plasma charges into a substrate 800 during the gatepatterning. After the gate patterning, a second dummy pattern 850 isformed in the second dummy pattern region C for discharging the plasmacharges into the substrate 800. In addition, a first butting contact816′ is formed to electrically connect a gate electrode 817 to thesubstrate 800, and a second butting contact 816″ is also formed toelectrically connect the gate electrode 817 to the substrate 800. Inaddition, a word line 830 is formed, which is configured with an ONOlayer 809 a, a gate electrode 817 and a spacer 824.

The above disclosed methods to form semiconductor memory devices may beused to fabricate any type or memory device. As described above, thedisclosed methods and structures may minimize the effect caused byplasma damage. Furthermore, as also described above, a butting contactis disposed in the vicinity of the cell array to electrically connectthe floating gate to the substrate. Thus, charge build-up of the etchingprocess is improved until the floating gate is completely etched by thepatterning process of the word line. Furthermore, by discharging chargesfrom the gates to the substrate, any damage of the tunnel oxide layermay be minimized. These and other such features may enhance thereliability of the memory device.

The above-disclosed subject matter is to be considered illustrative, andnot restrictive, and the appended claims are intended to cover all suchmodifications, enhancements, and other embodiments, which fall withinthe true spirit and scope of the present invention. Thus, to the maximumextent allowed by law, the scope of the present invention is to bedetermined by the broadest permissible interpretation of the followingclaims and their equivalents, and shall not be restricted or limited bythe foregoing detailed description.

1. A method for fabricating a nonvolatile memory device, the methodcomprising: forming an insulating layer and a conductive layer on asubstrate; forming an electrical connection path out of a portion of theconductive layer, through which the conductive layer is electricallyconnected to the substrate; and gate patterning the insulating layer andthe conductive layer.
 2. The method of claim 1, wherein the forming anelectrical connection path comprises forming a first contact or a secondcontact, the first contact directly connecting the portion of theconductive layer to the substrate, and the second contact not directlyconnecting the portion of the conductive layer to the substrate.
 3. Themethod of claim 1, wherein the gate patterning the insulating layer andthe conductive layer comprises: forming a gate pattern with theinsulating layer and the conductive layer stacked in a cell array regionof the substrate; and forming a dummy pattern in a vicinity of the cellarray region, the dummy pattern electrically connecting the conductivelayer to the substrate.
 4. The method of claim 1, wherein the gatepatterning the insulating layer and the conductive layer comprises:forming a gate pattern with the insulating layer and the conductivelayer stacked in a cell array region of the substrate; and forming atrench in a vicinity of the cell array region by removing at least aportion of the insulating layer and the conductive layer and etching aportion of the substrate.
 5. The method of claim 1, wherein the formingan insulating layer and a conductive layer on the substrate comprises:forming a first insulating layer on the substrate; forming a firstconductive layer on the first insulating layer; and forming a secondconductive layer on the first conductive layer.
 6. The method of claim5, wherein the forming an electrical connection path comprises: forminga contact hole by selectively removing a portion of the first insulatinglayer prior to forming the first conductive layer on the firstinsulating layer; and forming a contact through which the firstconductive layer is electrically connected to the substrate by formingthe first conductive layer on the first insulating layer such that thefirst conductive layer fills at least a portion of the contact hole. 7.The method of claim 5, wherein the forming an insulating layer and aconductive layer on the substrate further comprises forming a secondinsulating layer and a third conductive layer on the second conductivelayer.
 8. The method of claim 7, wherein the forming an electricalconnection path comprises: forming a first contact hole by selectivelyremoving a portion of the first insulating layer and the firstconductive layer; and forming a first contact through which the secondconductive layer is electrically connected to the substrate by formingthe second conductive layer on the first conductive layer such that thesecond conductive layer fills at least a portion of the first contacthole.
 9. The method of claim 8, wherein the forming an electricalconnection path further comprises: forming the second insulating layeron the second conductive layer; forming a second contact hole exposingthe second conductive layer by selectively etching the second insulatinglayer; and forming a second contact through which the third conductivelayer is electrically connected to the second conductive layer byforming the third conductive layer on the second insulating layer suchthat the third conductive layer fills at least a portion of the secondcontact hole.
 10. The method of claim 9, wherein the gate patterning theinsulating layer and the conductive layer comprises: forming a gatepattern that includes the insulating layer and conductive layer stackedin a cell array region of the substrate; forming a first dummy patternhaving the first contact and a second dummy pattern having the first andsecond contacts in a vicinity of the cell array region, wherein thefirst dummy pattern extends in a first direction and the second dummypattern extends in a second direction perpendicular to the firstdirection; and separating the second dummy pattern from the gatepattern.
 11. The method of claim 1, wherein the providing a substratecomprises forming a first well on the substrate and a second well in thefirst well, wherein both the substrate and second well have a firstconductive type, and the first well has a second conductive typeopposite to the first conductive type.
 12. The method of claim 11, priorto forming an electrical connection path, further comprising:selectively removing the insulating layer and the conductive layer toform a contact hole; and forming a third well of the first conductivetype in the second well below the contact hole, the third well having ahigher impurity concentration than the second well.
 13. A method forfabricating a nonvolatile memory device, the method comprising:providing a substrate including a cell array region and a dummy patternregion; forming a tunnel oxide layer and a floating gate layer on thesubstrate; forming a first butting contact out of a portion of thefloating gate layer through which the floating gate layer iselectrically connected to the substrate in the dummy pattern region;forming a blocking oxide layer and a control gate layer on the floatinggate layer; and gate patterning the control gate layer, the blockingoxide layer, the floating gate layer, and the tunnel oxide layer to forma word line in the cell array region and a first dummy pattern in thedummy pattern region, wherein the word line extends in a firstdirection, and wherein the first dummy pattern extends in the firstdirection and has the first butting contact.
 14. The method of claim 13,wherein the forming a first butting contact comprises: partiallyremoving the substrate of the dummy pattern region to form a contacthole; and filling at least a portion of the contact hole with thefloating gate layer such that the floating gate layer is directlyconnected to the substrate.
 15. The method of claim 13, wherein theforming a first butting contact comprises: forming a contact hole bypartially removing a tunnel oxide layer in the dummy pattern region suchthat the tunnel oxide layer of the dummy pattern region has a smallerthickness than the tunnel oxide layer of the cell array region; andfilling at least a portion of the contact hole with the floating gatelayer such that the floating gate layer is not directly connected to thesubstrate.
 16. The method of claim 13, wherein the gate patterningcomprises: forming a photoresist pattern on the substrate; andperforming an etching process using the photoresist pattern as a mask toform the word line in the cell array region and the first dummy patternhaving the first butting contact in the dummy pattern region, whereinthe word line includes the tunnel oxide layer, the floating gate layer,the blocking oxide layer and the control gate layer which are stacked insequence, and the first dummy pattern includes the tunnel oxide layer,the floating gate layer, the blocking oxide layer and the control gatelayer which are stacked in sequence.
 17. The method of claim 13, whereinthe gate patterning comprises: forming a photoresist pattern on thesubstrate, which does not cover the dummy pattern region; and performingan etching process using the photoresist pattern as a mask to form theword line including the tunnel oxide layer, the floating gate layer, theblocking oxide layer and the control gate layer which are stacked in thecell array region, and to remove the tunnel oxide layer, the floatinggate layer, the blocking oxide layer and the control gate layer whichare stacked in the dummy pattern region.
 18. The method of claim 13,further comprising forming a well electrically connected to the firstbutting contact in the substrate corresponding to the dummy patternregion.
 19. The method of claim 18, wherein the well has a higherimpurity concentration than the substrate.
 20. The method of claim 13,wherein the forming the blocking oxide layer and the control gate on thefloating gate layer further comprises forming a second butting contactelectrically connecting the control gate layer to the floating gatelayer in the dummy pattern region.
 21. The method of claim 20, whereinthe gate patterning further comprises: forming a second dummy patternhaving the first and second butting contacts, wherein the second dummypattern is connected to the word line in the dummy pattern region, andextends in a second direction that is substantially perpendicular to thefirst direction; and separating the second dummy pattern from the wordline.
 22. A method for fabricating a nonvolatile memory device, themethod comprising: providing a substrate including a cell array regionand a dummy pattern region; forming a charge storage layer and a gatelayer on the substrate; forming a butting contact out of a portion ofthe gate layer through which the gate layer is electrically connected tothe substrate in the dummy pattern region; and gate patterning the gatelayer and the charge storage layer to form a word line in the cell arrayregion and a first dummy pattern in the dummy pattern region, whereinthe word line extends in a first direction, and wherein the first dummypattern extends in the first direction and includes the butting contact.23. The method of claim 22, wherein the forming a butting contactcomprises: forming the charge storage layer, a first gate layer and asecond gate layer on the substrate and forming the butting contactelectrically connected to the substrate in the dummy pattern region, thebutting contact being formed from a portion of the first gate layer. 24.The method of claim 22, further comprising forming a well electricallyconnected to the butting contact in the substrate corresponding to thedummy pattern region.
 25. The method of claim 24, wherein the well has ahigher impurity concentration than the substrate.
 26. A nonvolatilememory device, comprising: a substrate including a cell array region anda first dummy pattern region; a word line extending in a first directionin the cell array region, and having a first insulating layer and afirst conductive layer; and a first dummy pattern including the firstinsulating layer, the first conductive layer and a first butting contactformed from a portion of the first conductive layer, wherein the firstbutting contact provides an electrical connection path connecting thefirst conductive layer to the substrate.
 27. The nonvolatile memorydevice of claim 26, wherein the first butting contact is one of a firstcontact directly contacting the substrate and a second contact notdirectly contacting the substrate and including a tunnel which runsthrough the first conductive layer and the substrate.
 28. Thenonvolatile memory device of claim 27, wherein the thickness of thefirst insulating layer interposed between the second contact and thesubstrate in the first dummy pattern region is smaller than thethickness of the first insulating layer in the cell array region. 29.The nonvolatile memory device of claim 26, wherein the substrateincludes a first well electrically connected to the first buttingcontact, and the first well has a higher impurity concentration than thesubstrate.
 30. The nonvolatile memory device of claim 28, wherein thesubstrate further comprises a second dummy pattern region in which asecond dummy pattern is formed such that the second dummy patternincludes the first insulating layer, the first conductive layer, and asecond butting contact providing an electrical connection pathconnecting the first conductive layer to the substrate, the secondbutting contact being formed from a portion of the first conductivelayer.
 31. The nonvolatile memory device of claim 30, wherein the secondbutting contact is one of a third contact directly contacting thesubstrate and a fourth contact not directly contacting the substrate andincluding a tunnel running through the first conductive layer and thesubstrate.
 32. The nonvolatile memory device of claim 31, wherein thethickness of the first insulating layer formed in the second dummypattern region and interposed between the fourth contact and thesubstrate is smaller than the thickness of the first insulating layerformed in the cell array region.
 33. The nonvolatile memory device ofclaim 30, wherein the substrate includes a second well electricallyconnected to the second butting contact, and the second well has ahigher impurity concentration than the substrate.
 34. The nonvolatilememory device of claim 30, wherein the first insulating layer has astructure in which a first dielectric layer and a charge storage layerare stacked in sequence.
 35. The nonvolatile memory device of claim 32,wherein the word line further comprises a second insulating layer and asecond conductive layer which are stacked on the first conductive layer,and the second dummy pattern further comprises the second insulatinglayer, the second conductive layer, and a third butting contact formedfrom a portion of the second conductive layer, the third butting contactproviding an electrical connection path connecting the second conductivelayer to the first conductive layer.
 36. A nonvolatile memory device,comprising: a substrate including a cell array region and a first dummypattern region; a word line extending in a first direction in the cellarray region, and including a first insulating layer and a firstconductive layer; and a trench formed by removing a portion of thesubstrate in the first dummy pattern region, and extending in the firstdirection.
 37. The nonvolatile memory device of claim 36, wherein thesubstrate further comprises a second dummy pattern region in which adummy pattern extends in a second direction perpendicular to the firstdirection, and includes the first insulating layer, the first conductivelayer, and a first butting contact providing an electrical connectionpath connecting the first conductive layer to the substrate.
 38. Thenonvolatile memory device of claim 37, wherein the word line furtherincludes a second insulating layer and a second conductive layer stackedon the first conductive layer, and the second dummy pattern furthercomprises the second insulating layer, the second conductive layer, anda third butting contact formed from a portion of the second conductivelayer, the third butting contact providing an electrical connection pathconnecting the second conductive layer to the first conductive layer.